The present technology relates to a phase synchronization apparatus, a phase synchronization method and a phase synchronization program. More specifically, the present technology relates to a phase synchronization apparatus capable of synchronizing a plurality of symbols at a higher speed on the basis of received signals sampled asynchronously with the symbol period by carrying out concurrent processing to generate the symbols and relates to a phase synchronization method adopted by the apparatus as well as a phase synchronization program implementing the method.
FIG. 1 is a block diagram showing a typical configuration of a radio communication system.
As shown in FIG. 1, the radio communication system is configured to include a signal transmitting apparatus 1 and a signal receiving apparatus 2. The signal transmitting apparatus 1 is configured to include a transmitting-side base band block 11, a transmitting-side RF circuit 12 and an antenna 13.
The transmitting-side base band block 11 is configured to include an error-correction coding circuit 21, a header/preamble insertion circuit 22, a modulation circuit 23, a transmitting-side filter 24 and a D/A (Digital/Analog) converter 25. Transmission data to be transmitted is supplied to the transmitting-side base band block 11 employed in the signal transmitting apparatus 1.
The error-correction coding circuit 21 generates parity bits for typically an error correction purpose on the basis of the data being transmitted and adds the parity bits to the data being transmitted in an error correction coding process. The error-correction coding circuit 21 supplies the result of the error correction coding process carried out on the transmission data being transmitted to the header/preamble insertion circuit 22.
The header/preamble insertion circuit 22 inserts a header and/or a preamble into the transmission data received from the error-correction coding circuit 21. The header and/or the preamble include a variety of parameters. The header/preamble insertion circuit 22 supplies the transmission data including the header and/or the preamble to the modulation circuit 23.
The modulation circuit 23 carries out modulation processing such as the QPSK (Quadrature Phase Shift Keying) modulation processing or the BPSK (Binary Phase Shift Keying) modulation processing in order to convert the transmission data received from the header/preamble insertion circuit 22 into a sequence of transmission symbols separated from each other by a period Ts. The modulation circuit 23 supplies each of the transmission symbols obtained as a result of the conversion to the transmitting-side filter 24.
The transmitting-side filter 24 carries out a filtering process on the transmission symbols received from the modulation circuit 23 in order to impose limits on the transmission band and supplies transmission symbols obtained as a result of the filtering process to the D/A converter 25.
The D/A converter 25 carries out D/A conversion processing on the transmission symbols received from the transmitting-side filter 24 and supplies an analog base band signal obtained as a result of the D/A conversion processing to the transmitting-side RF circuit 12.
The transmitting-side RF circuit 12 superposes the analog base band signal received from the D/A converter 25 on a carrier having a frequency determined in advance, supplying the analog base band signal and the carrier to the antenna 13 for transmitting the analog base band signal and the carrier to the signal receiving apparatus 2.
The signal receiving apparatus 2 is configured to include an antenna 31, a receiving-side RF circuit 32 and a receiving-side base band block 33. The receiving-side base band block 33 is configured to include an A/D converter 41, a receiving-side filter 42, a phase synchronization circuit 43, a demodulation circuit 44 and an error correction code decoding circuit 45. The antenna 31 receives the RF transmission signal transmitted by the signal transmitting apparatus 1 and supplies the RF signal to the receiving-side RF circuit 32 by way of the antenna 13.
The receiving-side RF circuit 32 converts the RF signal received from the antenna 31 into an analog base band signal and supplies the analog base band signal to the receiving-side base band block 33.
The A/D converter 41 employed in the receiving-side base band block 33 carries out sampling processing on the analog base band signal received from the receiving-side RF circuit 32 at a sampling period Tp asynchronous with a symbol period Ts. The A/D converter 41 supplies data obtained as a result of the sampling processing to the receiving-side filter 42 as a received signal.
The receiving-side filter 42 carries out a filtering process on the received signal supplied thereto by the A/D converter 41 and supplies the result of the filtering process to the phase synchronization circuit 43.
The phase synchronization circuit 43 is configured to function as typically an FIR (Finite Impulse Response) filter. The phase synchronization circuit 43 implements symbol synchronization on the basis of the received signal supplied thereto by the receiving-side filter 42. The phase synchronization circuit 43 carries out interpolation processing in order to find received symbols from the received signal and then supplies the received symbols to the demodulation circuit 44.
The demodulation circuit 44 carries out demodulation processing by adoption of a demodulation method corresponding to the modulation method adopted by the signal transmitting apparatus 1 in order to demodulate the received symbols. Typical examples of the demodulation processing are the QPSK demodulation processing and the BPSK demodulation processing. Then, the demodulation circuit 44 supplies received data obtained as a result of the demodulation processing to the error correction code decoding circuit 45.
The error correction code decoding circuit 45 carries out error correction processing on the received data supplied thereto by the demodulation circuit 44 and outputs the received data obtained as a result of the error correction processing to an external data recipient.
The technique adopted by the signal receiving apparatus 2 to implement symbol synchronization is a technique making use of an interpolation FIR filter to find received symbols from received signals obtained as a result of sampling the analog base band signal at a sampling period Tp asynchronous with a symbol period Ts as described above. In this case, the A/D converter 41 carries out a sampling process at a constant clock period. It is to be noted that, as a technique adopted by the signal receiving apparatus 2 to implement symbol synchronization on the receiving side of the radio communication system, there is also a technique in accordance with which the sampling phase of the A/D converter is controlled and the output of the A/D converter is taken as received symbols.
The former technique adopted by the signal receiving apparatus 2 has merits that it is not necessary to control the sampling frequency of the A/D converter 41 and it is possible to eliminate a delay introduced by a phase error feedback.
In addition, the signal receiving apparatus 2 also has a merit that, since the phase synchronization circuit 43 is configured as a digital circuit handling no analog signal, the function of the phase synchronization circuit 43 can be verified by carrying out only digital-circuit verification processing. If the phase synchronization circuit 43 is configured as mixed circuits including analog and digital circuits for example, the characteristic of the analog circuit particularly changes with the temperature so that it is difficult to verify the function of the analog circuit. In the case of this signal receiving apparatus 2, however, the function of the phase synchronization circuit 43 can be verified by adoption of a simpler technique.
The method described above as a method to implement symbol synchronization is also described in documents such as Japanese Patent, Laid-Open No. 2006-338726 (hereinafter referred to as Patent Document 1), Japanese Patent Laid-Open No. 2007-26596 (hereinafter referred to as Patent Document 2) and U.S. Pat. No. 5,309,484.
FIG. 2 is a block diagram showing a typical configuration of the phase synchronization circuit 43 shown in FIG. 1.
As shown in FIG. 2, the phase synchronization circuit 43 is configured to include an interpolation FIR filter 61 and a signal processing circuit 62. The signal processing circuit 62 is configured to include a phase-error detection circuit 71, a loop filter 72 and an NCO (Numerical Control Oscillator) 73. The received signal is supplied by the receiving-side filter 42 to the interpolation FIR filter 61 by way of an input terminal 51.
The interpolation FIR filter 61 carries out interpolation processing by making use of the received signal and a phase offset Φk received from the NCO 73, outputting a received symbol yk to the demodulation circuit 44 by way of a received-symbol output terminal 52. The interpolation FIR filter 61 also supplies the received symbol yk to the phase-error detection circuit 71 employed in the signal processing circuit 62.
The NCO 73 also outputs an enable signal ek to a circuit at the immediately succeeding stage. The immediately succeeding stage makes use of the enable signal ek for determining whether or not the received symbol yk is to be processed. The received symbol yk generated by the interpolation FIR filter 61 can be said to be a candidate for a received symbol.
It is also possible to provide a configuration in which the enable signal ek is also supplied to the interpolation FIR filter 61. In this case, the interpolation FIR filter 61 carries out the interpolation processing on the received signal only if the value of the enable signal ek indicates that the interpolation processing is to be carried out.
FIG. 3 is a diagram showing relations between the analog base band signal, the received signals and the received symbols.
A solid line shown in FIG. 3 represents the waveform of the analog base band signal supplied to the A/D converter 41. Each of white circles represents the received signal obtained as a result of the sampling process carried out by the A/D converter 41 on the analog base band signal. The received signals are supplied to the receiving-side filter 42 for carrying out a proper filtering process on the received signals. Each of black circles represents a received symbol. An interval between two adjacent white circles is referred to as a sampling period Tp whereas an interval between two adjacent black circles is referred to as a symbol period Ts.
As described above, the interpolation FIR filter 61 carries out the interpolation processing. In the interpolation processing, the phase of the received signal is corrected on the basis of a phase offset Φk found by the NCO 73 and the corrected phase is taken as the phase of a received symbol in inference of the value of the received symbol.
The reader is advised to refer back to FIG. 2. In the signal processing circuit 62, the NCO 73 also outputs the enable signal ek to the phase-error detection circuit 71. The phase-error detection circuit 71 detects a phase error dk on the basis of the received symbol yk output by the interpolation FIR filter 61 and the enable signal ek output by the NCO 73. The phase-error detection circuit 71 supplies the phase error dk to the loop filter 72.
For the purpose of stabilizing the feedback loop, the loop filter 72 carries out a filtering process on the sequence of phase errors dk, outputting a phase-error correction value lk to the NCO 73.
On the basis of the phase-error correction value lk, the NCO 73 computes a phase offset Φk between the received signal and the received symbol, outputting the phase offset Φk to the interpolation FIR filter 61. In addition, the NCO 73 also finds the value of the enable signal ek, outputting the enable signal ek representing the found value to the phase-error detection circuit 71 and a circuit at the immediately succeeding stage by the way of the enable-signal output terminal 53.
As described above, the phase synchronization circuit 43 carries out feedback control to update the phase offset Φk on the basis of the received symbol yk so as to establish symbol synchronization. The phase synchronization circuit 43 shown in FIG. 2 functions as the so-called interpolation-type phase-synchronization circuit having a serial configuration for outputting one received symbol yk and an enable signal ek at every time k for a received signal which is obtained as one sample.
Floyd M. Gardner, “Interpolation in digital modems-I: Fundamentals,” IEEE Trans. Commun., vol 41, pp. 501-507, March 1993 (hereinafter referred to as Non-Patent Document 1) and Zi-Ning Wu and John M. Cioffi, “A MMSE Interpolated Timing Recovery Scheme for the Magnetic Recording Channel,” IEEE International Conference on Communications 1977, pp. 1625-1629, 1997 (hereinafter referred to as Non-Patent Document 2) describe representative algorithms used in the phase-synchronization circuit having a serial configuration for processing a received signal for every sampling period Tp in order to output a received symbol. These algorithms are described as follows.
At a time k which is a sampling time where k is a natural number, the interpolation FIR filter 61 shown in FIG. 2 finds a received symbol yk by making use of a phase offset Φk computed at the immediately preceding time k−1. The phase offset Φk is an offset normalized by making use of the sampling period Tp. The phase offset Φk has a value in the following range: 0≦Φk<1.
The phase-error detection circuit 71 receives the received symbol yk and the enable signal ek, finding a phase error dk in accordance with Eq. (1) given below. Δk used in Eq. (1) is expressed by Eq. (2) also given below.dk=ek·Kd·Δk  (1)Δk=kτ(yk· y′k−1− yk·y′k−1)  (2)
In addition, at the time k, if the enable signal ek is 1, the phase-error detection circuit 71 outputs the phase error dk. If the enable signal ek is 0, on the other hand, the phase-error detection circuit 71 outputs 0. That is to say, the phase-error detection circuit 71 outputs the phase error dk or 0 and, at the same time, updates an internal variable y′k in accordance with Eq. (3) as follows.
                              y          k          ′                =                  {                                                                                          y                    k                                    ,                                                                                                  if                    ⁢                                                                                  ⁢                                          e                      k                                                        =                  1                                                                                                                          y                                          k                      -                      1                                        ′                                    ,                                                            else                                                                        (        3        )            
In the above equation, ek∈{0, 1} denotes the enable signal ek computed at the sampling time (k−1) for the received symbol yk. In addition, reference notation Kd used in Eq. (1) denotes a gain set for the phase-error detection circuit 71 whereas reference notation kτ used in Eq. (2) denotes a constant. Reference notation yk put under reference notation ‘−’ in Eq. (2) denotes the (hard determination value) of the received symbol yk.
The loop filter 72 receives the phase error dk from the phase-error detection circuit 71 and finds a phase-error correction value lk from the phase error dk. If the phase synchronization circuit 43 shown in FIG. 2 is configured to function as a second-order feedback system, the phase-error correction value lk is updated typically in accordance with Eq. (4) given as follows.
                              I          k                =                  μ          ⁡                      (                                                            K                  p                                ⁢                                  d                  k                                            +                                                K                  I                                ⁢                                                      ∑                                          i                      =                      1                                        k                                    ⁢                                      d                    i                                                                        )                                              (        4        )            
In Eq. (4), reference notation Kp denotes a coefficient for a proportional term of the loop filter 72 whereas reference notation KI denotes a coefficient for an integral term of the loop filter 72. Reference notation μ denotes the ratio Ts/Tp (that is, μ≡Ts/Tp) which is the symbol period Ts normalized by the sample period Tp. In general, the A/D converter 41 carries out the sampling process in an over-sampling state. Thus, the value of the ratio μ is a real number not smaller than 1.
The NCO 73 updates the phase offset Φk+1, which will be used at the time k+1 in the interpolation FIR filter 61, in accordance with Eq. (5) given as follows.
                              ϕ                      k            +            1                          =                  {                                                                                                                ϕ                      k                                        +                                          (                                              μ                        -                        1                                            )                                        +                                          l                      k                                                        ,                                                                                                  if                    ⁢                                                                                  ⁢                                          ϕ                      k                                                        <                  1                                                                                                                                                ϕ                      k                                        -                    1                                    ,                                                            else                                                                        (        5        )            
In addition, the NCO 73 computes the enable signal ek+1 in accordance with Eq. (6) given below. The enable signal ek+1 is associated with the received symbol yk+1 output by the interpolation FIR filter 61 at the time (k+1). That is to say, if the value of the enable signal ek+1 is 1, the received symbol yk+1 is handled as a symbol to be processed in a circuit provided at the immediately succeeding stage.
                              e                      k            +            1                          =                  {                                                                      1                  ,                                                                                                  if                    ⁢                                                                                  ⁢                                          ϕ                                              k                        +                        1                                                                              <                  1                                                                                                      0                  ,                                                            else                                                                        (        6        )            
FIG. 4 is a diagram showing a typical configuration of the NCO 73 shown in FIG. 2.
An addition circuit 91 adds (μ−1) received from an input terminal 81 to the phase-error correction value lk received from an input terminal 82 in order to generate a sum. The expression (μ−1) has a value set for the NCO 73. On the other hand, the loop filter 72 supplies the phase-error correction value lk by way of the input terminal 82.
A select circuit 92 selects the value 0 if the MSB (most significant bit) of the phase offset Φk stored in a buffer 94 is 1. However, the select circuit 92 selects the sum generated by the addition circuit 91 if the MSB of the phase offset Φk stored in the buffer 94 is 0.
An addition circuit 93 adds the value selected by the select circuit 92 to a value represented by the bit string of the phase offset Φk in order to produce a sum. However, the bit string to be added to the output of the select circuit 92 excludes the most significant bit of the bit string. That is to say, the addition circuit 91, the select circuit 92 and the addition circuit 93 carry out operations represented by Eq. (5).
The sum generated by the addition circuit 93 is stored in the buffer 94 as the phase offset Φk. The most significant bit of the bit string of this sum is supplied to an inversion circuit 95. The most significant bit of the bit string of this sum is inverted by the inversion circuit 95 in order to produce the enable signal ek+1. The inversion circuit 95 supplies the enable signal ek+1 to an enable-signal output terminal 83. On the other hand, the addition circuit 93 supplies the string bits following the most significant bit on the string of bits to a phase-offset output terminal 84 as the phase offset Φk+1.
Algorithms for finding values in the phase synchronization circuit having a serial configuration as described above are explained in Non-Patent Documents 1 and 2.
The reader is advised to keep in mind that it is also possible to configure a recording/reproduction system from a recording apparatus provided with the transmitting-side base band block 11 and from a reproduction apparatus provided with the receiving-side base band block 33. In this case, the reproduction apparatus reproduces data, which has been recorded by the recording apparatus on a recording medium, from the recording medium.
By the way, in recent years, there are rising demands for higher data transfer speeds in communication systems and recording/reproduction systems. Such demands set an increasing trend of the symbol frequency. If a phase synchronization circuit having a serial configuration as described above is used, the symbol frequency can be increased to a demanded value by raising the operation frequency of the circuit. However, the operation frequency of the circuit has an upper limit imposed by, among others, semiconductor processes. Thus, in some cases, the symbol frequency cannot be increased to the demanded value.
In order to solve the problem described above, a technique referred to as an N-signals concurrent processing technique for implementing a phase synchronization circuit has been introduced in recent years. In accordance with this technique which is adopted in several cases, the phase synchronization circuit is operated at a clock frequency equal to 1/N times the sampling frequency and N received signals are processed in N-signals concurrent processing for every clock period. In this case, N is an integer not smaller than 2. In an interpolation-type phase synchronization circuit adopting the N-signals concurrent processing technique, N received symbols and N enable signals each generated for one of the N received symbols are output for every clock period.
FIG. 5 is a diagram showing a typical configuration of an N-signals concurrent-processing phase synchronization circuit implemented by adoption of algorithms identical with the algorithms adopted by the phase synchronization circuit having the serial configuration described above.
As shown in FIG. 5, the phase synchronization circuit 43 functioning as an N-signals concurrent-processing phase synchronization circuit is configured to include interpolation FIR filters 111-1 to 111-N and signal processing circuits 112-1 to 112-N. The interpolation FIR filters 111-1 to 111-N and the signal processing circuits 112-1 to 112-N are connected alternately to each other in a nose-to-tail form. Each of the signal processing circuits 112-1 to 112-N has a configuration identical with the configuration of the signal processing circuit 62 shown in FIG. 2. The receiving-side filter 42 supplies a received signal to each of the interpolation FIR filters 111-1 to 111-N by way of an input terminal 101.
The interpolation FIR filter 111-1 carries out interpolation processing by making use of a phase offset Φk found by the signal processing circuit 112-N in order to output a received symbol yk. The received symbol yk output by the interpolation FIR filter 111-1 is supplied to a received-symbol output terminal 102 and the signal processing circuit 112-1 as a received symbol at the time k.
In the same way as the signal processing circuit 62 shown in FIG. 2, the signal processing circuit 112-1 computes the phase offset Φk+1 and the enable signal ek+1 on the basis of the received symbol yk and the enable signal ek generated by the signal processing circuit 112-N. The signal processing circuit 112-1 outputs the phase offset Φk+1 to the interpolation FIR filter 111-2 and the enable signal ek+1 to the signal processing circuit 112-2 as well as an enable-signal output terminal 103.
The interpolation FIR filter 111-2 carries out interpolation processing by making use of a phase offset Φk+1 found by the signal processing circuit 112-1 in order to output a received symbol yk+1. The received symbol yk+1 output by the interpolation FIR filter 111-2 is supplied to the received-symbol output terminal 102 and the signal processing circuit 112-2 as a received symbol at the time (k+1).
The signal processing circuit 112-2 computes the phase offset Φk+2 and the enable signal ek+2 on the basis of the received symbol yk+1 and the enable signal ek+1 generated by the signal processing circuit 112-1. The signal processing circuit 112-2 outputs the phase offset Φk+2 to the immediately succeeding stage and the enable signal ek+2 to the immediately succeeding stage as well as the enable-signal output terminal 103.
An interpolation FIR filter provided at every later stage also carries out the same processing described above whereas a signal processing circuit provided at every later stage also carries out the same processing described above. The interpolation FIR filter 111-N carries out interpolation processing on the received signal by making use of a phase offset Φk+N−1 found by a signal processing circuit provided at the immediately preceding stage in order to output a received symbol yk+N−1. The received symbol yk+N−1 output by the interpolation FIR filter 111-N is supplied to the received-symbol output terminal 102 and the signal processing circuit 112-N as a received symbol at the time (k+N−1).
The signal processing circuit 112-N computes the phase offset Φk and the enable signal ek on the basis of the received symbol yk+N−1 and the enable signal ek+N−1 generated by the signal processing circuit 112-N-1 not shown in FIG. 5. The signal processing circuit 112-N outputs the phase offset Φk to the interpolation FIR filter 111-1 and the enable signal ek to the signal processing circuit 112-1 as well as the enable-signal output terminal 103.
By adopting the configuration described above, the size of the phase synchronization circuit 43 functioning as an N-signals concurrent-processing phase synchronization circuit is about N times the size of the phase synchronization circuit 43 having the serial configuration. That is to say, the size of the phase synchronization circuit 43 is undesirably very large. In addition, the amount of processing carried out per clock period in the phase synchronization circuit 43 is also about N times the amount of processing carried out per clock period in the phase synchronization circuit 43 having the serial configuration. Thus, it is difficult to set the maximum operation frequency of the phase synchronization circuit 43 at a value at least (1/N) times the maximum operation frequency of the phase synchronization circuit 43 having the serial configuration.
Patent Document 1 discloses algorithms for implementing a phase synchronization circuit downsized to function as an N-signals concurrent-processing phase synchronization circuit. The algorithms disclosed in Patent Document 1 are explained as follows.
The configuration of an N-signals concurrent-processing phase synchronization circuit adopting the algorithms disclosed in Patent Document 1 is itself identical with the configuration of the phase synchronization circuit 43 shown in FIG. 2. The unit of data processed in each circuit is an N-data unit.
Each of the interpolation FIR filter 61, the phase-error detection circuit 71 and the loop filter 72 carries out processing based on algorithms identical with the algorithms adopted by their respective counterparts in the phase synchronization circuit 43 having the serial configuration.
On the other hand, the NCO 73 updates N phase offsets and N enable signals in accordance with following Eqs. (7) and (8) respectively at the time k.
                              ϕ                      k            +            i                          =                  {                                                                                                                ϕ                                              k                        +                        i                        -                        1                                                              +                                          (                                              μ                        -                        1                                            )                                        +                                          l                                              k                        +                        i                        -                        1                        -                        N                                                                              ,                                                                                                  if                    ⁢                                                                                  ⁢                                          ϕ                                              k                        +                        i                        -                        1                                                                              <                  1                                                                                                                                                ϕ                                              k                        +                        i                        -                        1                                                              -                    1                                    ,                                                            else                                                                        (        7        )                                          e                      k            +            i                          =                  {                                                                      1                  ,                                                                                                  if                    ⁢                                                                                  ⁢                                          ϕ                                              k                        +                        i                                                                              <                  1                                                                                                      0                  ,                                                            else                                                                        (        8        )            
In Eqs. (7) and (8), notation i is an integer having a value in the range 1 to N. It is to be noted that Eqs. (7) and (8) are described in Patent Document 1 as equations for updating the phase offset and the enable signal respectively.
By comparing Eqs. (5) and (7) with each other, the following difference becomes obvious. In the phase synchronization circuit having the serial configuration, the phase-error correction value lk is used in the computation of the phase offset Φk used in the interpolation processing carried out in order to generate the received symbol at the time (k+1). In the N-signals concurrent-processing interpolation-type phase synchronization circuit disclosed in Patent Document 1, on the other hand, the phase-error correction value lk is used in the computation of the phase offset Φk+N used in the interpolation processing carried out in order to generate the received symbol at the time (k+N).
In general, in a phase synchronization circuit carrying out feedback control, if the delay to the reflection of information obtained from an output result becomes long, the phase synchronization circuit displays poor performance that the range of synchronizable symbol frequencies becomes narrow.
FIG. 6 is a diagram showing the circuit configuration of the NCO 73 updating the phase offset by adoption of the algorithm disclosed in Patent Document 1. The circuit configuration of the NCO 73 shown in FIG. 6 is obtained by interconnecting four configurations, which are each shown in FIG. 4, in parallel. That is to say, the circuit configuration of the NCO 73 shown in FIG. 6 is obtained by setting N at 4 (that is, N=4). The circuit configuration of the NCO 73 shown in FIG. 6 is explained by properly omitting explanation of what have been described before as follows. The loop filter 72 supplies phase-error correction values lk, lk−1, lk−2 and lk−3 output thereby as a four-data unit to respectively input terminals 122-1, 122-2, 122-3 and 122-4.
An addition circuit 141-1 adds (μ−1) received from an input terminal 121 to the phase-error correction value lk in order to generate a sum. A select circuit 142-1 selects the value 0 or the sum in accordance with the most significant bit of a bit string found on the basis of the phase-error correction value lk−1.
An addition circuit 143-1 adds the value selected by the select circuit 142-1 to a value represented by the bit string found on the basis of the phase-error correction value in order to produce a sum. However, the bit string to be added to the output of the select circuit 142-1 excludes the most significant bit of the bit string. The sum generated by the addition circuit 143-1 is stored in a buffer 145. The sum stored in the buffer 145 will be used in the computation of the phase offset Φk+1 and the enable signal ek+1.
The most significant bit of the sum is inverted by the inversion circuit 144-1 in order to produce the enable signal ek+4. The inversion circuit 144-1 supplies the enable signal ek+4 to an enable-signal output terminal 131-1. On the other hand, the addition circuit 143-1 supplies the string bits following the most significant bit of the sum to a phase-offset output terminal 132-1 as the phase offset Φk+4.
The NCO 73 having the circuit configuration shown in FIG. 6 is capable of computing phase offsets to be used in the interpolation processing carried out on four received signals. However, the computation itself is carried out as serial processing so that it is difficult to increase the speed of the operation.
In the computation of the phase offset Φk+4 for example, a value found on the basis of the phase-error correction value lk−1 is demanded. By the same token, in the computation of the phase offset Φk+3, a value found on the basis of the phase-error correction value lk−2 is demanded. In the same way, in the computation of the phase offset Φk+2, a value found on the basis of the phase-error correction value lk−3 is demanded. Similarly, in the computation of the phase offset Φk+1, a value found on the basis of the phase-error correction value lk is demanded.
The following description explains algorithms each disclosed in Patent Document 2 to serve as an algorithm for raising the speed of the operation carried out by an N-signals concurrent-processing phase synchronization circuit.
Patent Document 2 discloses the circuit configuration of a two-signals concurrent-processing interpolation-type phase synchronization circuit and a method of extending the circuit configuration in order to construct an N-signals concurrent-processing interpolation-type phase synchronization circuit for N≧3. In addition, Patent Document 2 also discloses an algorithm for computing a phase offset Φ′k+i to be used in N interpolation FIR filters where 1≦i≦N in accordance with Eq. (9) given below. In Eq. (9), an inferred symbol period (μ+kk) is a value obtained as a result of correcting the ratio μ by making use of the phase-error correction value lk.Φ′k+i=(Φ′k+i)mod(μ+lk)  (9)
The algorithms disclosed in Patent Document 2 are algorithms each used for computing N phase offsets at the same time independently of each other. In the computation of N phase offsets the same inferred symbol period (μ+lk) common to all the N phase offsets Φ′k+i is used.
In a configuration for computing three phase offsets at the same time for example, as shown in FIG. 7, there are intervals n, (n+1) and (n+2) during which the three phase offsets are computed. The intervals n, (n+1) and (n+2) are intervals for symbols to be found. During each of the intervals, the ratio μ serving as a normalized symbol period is corrected to the same period (μ+lk) to be used in the computation of each of the phase offset. Each white circle shown in FIG. 7 represents a received symbol.
That is to say, in the operation to compute the phase offset Φ′k+i by making use of Eq. (9), the phase of the received signal is compared with the symbol phase corrected by making the phase-error correction value lk proportional to the symbol-interval count N, that is, by making the phase-error correction value lk proportional to the length of the elapsed time.
In addition, the algorithms disclosed in Non-Patent Document 1 are algorithms for inferring a phase offset between a received symbol yk and a received symbol succeeding the received symbol yk. On the other hand, the algorithms disclosed in Patent Document 2 are algorithms for inferring a phase offset between a received symbol yk and a received symbol preceding the received symbol yk.
In an operation to compute enable signals ek+1 and ek+2 by carrying out two-signals concurrent processing, Eqs. (10) and (11) given below are used respectively. Eqs. (10) and (11) are equations expressing the computations based on the algorithms disclosed in Patent Document 2.
                                              ⁢                              e                          k              +              1                                =                      {                                                                                1                    ,                                                                                                              if                      ⁢                                                                                          ⁢                                              ϕ                                                  k                          +                          1                                                ′                                                              >                                          μ                      +                                              l                        k                                                                                                                                                              0                    ,                                                                    else                                                                                        (        10        )                                          e                      k            +            2                          =                  {                                                                      1                  ,                                                                              if                  ⁢                                                                          ⁢                                      {                                                                  (                                                                              ϕ                            k                            ′                                                    +                          1                                                )                                            ⁢                                                                                          ≤                                                                        (                                                      μ                            +                                                          l                              k                                                                                )                                                ⁢                                                                                                  ⁢                        and                        ⁢                                                                                                  ⁢                                                  (                                                                                    ϕ                              k                              ′                                                        +                            2                                                    )                                                                    >                                              (                                                  μ                          +                                                      l                            k                                                                          )                                                              }                                    ⁢                                                                          ⁢                  or                                                                                                                                                                                    {                                                            (                                                                        ϕ                                                      k                            +                            1                                                    ′                                                +                        1                                            )                                        >                                                                  (                                                  μ                          +                                                      l                            k                                                                          )                                            ⁢                                                                                          ⁢                      and                      ⁢                                                                                          ⁢                                              (                                                                              ϕ                            k                            ′                                                    +                          2                          -                                                      (                                                          μ                              +                                                              l                                k                                                                                      )                                                                          )                                                              >                                          (                                              μ                        +                                                  l                          k                                                                    )                                                        }                                                                                                      0                  ,                                                            else                                              }                                    (        11        )            
In Eq. (11) for computing the enable signal ek+2, it is necessary to know the result of determining whether or not the relation (Φ′k+i>μ+lk) for the enable signal ek+1 holds true. Thus, in an operation to compute the enable signal ek+i (where 1<i≦N) for N≧3, it is assumed that the results of computing the enable signals ek+1 to ek+i−1 are demanded.